A collection of academic works of interest dealing with computing and associated tools.

Computer Architecture
2017 In-Datacenter Performance Analysis of a Tensor Processing Unit​TM
2017 SAIL – A language for expressing multiprocessor ISA descriptions ( The Sail instruction-set semantics specification language )
2016 Trustworthy Specifications of ARM© v8-A and v8-M System Level Architecture
2016 The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V
2015 Branch Prediction and the Performance of Interpreters – Don’t Trust Folklore
2015 Instruction-set Architecture Synthesis for VLIW Processors
2015 Efficient Out-of-Order Execution of Guarded ISAs
2010 The Instruction-Set Extension Problem: A Survey
2007 Functional Principles of Cache Memory
2007 What Every Programmer Should Know About Memory
2004 Reflections on the Memory Wall
2002 Approaches to Addressing the Memory Wall
2001 A Decade of Reconfigurable Computing: a Visionary Retrospective
1996 Beyond RISC – The Post-RISC Architecture
1996 LISA – Machine Description Language and Generic Machine Model for HW/SW Co-Design
1995 Describing Instruction Set Processors Using nML
1994 Speculative Execution and Instruction-Level Parallelism
1992 Instruction-Level Parallel Processing: History, Overview and Perspective
1988 A methodology for automated design of computer instruction sets
1984 VLSI Processor Architecture
1980 The Case for the Reduced Instruction Set Computer
1973 Threaded Code
Architecture Description Languages
LISA – Machine Description Language for Cycle Accurate Models of Programmable DSP Architectures
The ARM Scalable Vector Extension
Computer Architecture at the University of Washington
2016 QBox: an industrial solution for virtual platform simulation using QEMU and SystemC TLM-2.0 (see also)
2016 rv8: a high performance RISC-V to x86 binary translator
2016 High Speed Cycle-Accurate Processor Simulation Through Ahead of Time Compilation
2016 A Comparison of x86 Computer Architecture Simulators
2014 Contributions à la traduction binaire dynamique : support du parallélisme d’instructions et génération de traducteurs optimisés
2013 ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems
2011 System on Chip – Design and Modelling
2011 Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator
2011 Fast Instruction-Accurate Simulation with SimNML
2011 System On Chip modeling with SystemC/TLM
2011 An Overview of Computer Architecture and System Simulation
2010 SimSoC: A full system simulation software for embedded systems
Fast and Accurate Simulation using the LLVM Compiler Framework
2009 A Versatile Generator of Instruction Set Simulators and Disassemblers
2008 Fast Cycle-Approximate Instruction Set Simulation
2008 SimSoC: A SystemC TLM integrated ISS for full system simulation
2008 Generation of Executable Representation for Processor Simulation with Dynamic Translation
2005 Transaction Level Modeling With SystemC
2004 Improvement of compiled instruction set simulator by increasing flexibility and reducing compile time
2003 Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation
2002 Effective Support of Simulation in Computer Architecture Instruction
2001? MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems
2000 The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool
1997 Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign
1995 Fast Simulation of Computer Architecture
1994 Some Efficient Techniques for Simulating Memory
1994 A Compact Intermediate Format for SIMICS
1994 Simulating Computer Architecture
1993 Shade: A Fast Instruction-Set Simulator for Execution Profiling
1991 Compiled Instruction Set Simulation
1990? Some Efficient Architecture Simulation Techniques
Generation of Hardware Machine Models from Instruction Set Descriptions
1974 Formal Requirements for Virtualizable Third Generation Architectures
2009 Testing CPU emulators
Computer Vision
2008 Visual SLAM

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