January 17, 2019February 4, 2020 by Jean-François Monestier

About RISC-V ISA

Some pointers dealing with the RISC-V ISA.

Generalities
Design of the RISC-V Instruction Set Architecture

Performance
Comparing RISC-V, ARM, and x86 on SPECInt 2006 – How to make a high-performance RISC-V processor using macro-op fusion
The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V

Codesize
Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed
RISC-V Compressed Extension
RISC-V Compiler Performance Part 1: Code Size Comparisons
RISC-V Code Size Comparison with Cortex M
Linux Logo
A Compression Instruction Set Design based on RISC-V for Network Packet Forwarding
RISC-V ISA: Understanding Limitations and Methods to improve code density & performance
Reduce Static Code Size and Improve RISC-V Compression
Optimizing RISC-V Software for Code Density – Version 1.0

Security
Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing
XCrypto: a cryptographic ISE for RISC-V