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Jean-François Monestier

Graduate Engineer – Engineering Degree in Computer Science – INSA Rennes – INFO94

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Posted on January 17, 2019February 4, 2020 by Jean-François Monestier

About RISC-V ISA

Some pointers dealing with the RISC-V ISA.

Generalities
Design of the RISC-V Instruction Set Architecture
Performance
Comparing RISC-V, ARM, and x86 on SPECInt 2006 – How to make a high-performance RISC-V processor using macro-op fusion
The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V
Codesize
Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed
RISC-V Compressed Extension
RISC-V Compiler Performance Part 1: Code Size Comparisons
RISC-V Code Size Comparison with Cortex M
Linux Logo
A Compression Instruction Set Design based on RISC-V for Network Packet Forwarding
RISC-V ISA: Understanding Limitations and Methods to improve code density & performance
Reduce Static Code Size and Improve RISC-V Compression
Optimizing RISC-V Software for Code Density – Version 1.0
Security
Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing
XCrypto: a cryptographic ISE for RISC-V

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About This Site

I'm Jean-François Monestier, and you've reached my personal homepage.

I'm a Senior Software Engineer currently working at STMicroelectronics, in the Embedded Computing Solutions organization, this team being accountable for the architecture, the design, the marketing and the support of the STxP70 processor and associated tools.

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