Welcome

I’m Jean-François Monestier, and you’ve reached my personal homepage.

I’m a Senior Software Engineer, currently working at STMicroelectronics in the Embedded Computing Solutions organization, this team being accountable for the architecture, the design, the marketing and the support of the STxP70 processor and associated tools.

The STxP70 processor is a proprietary, cost-effective, configurable and customizable synthesizable dual-issue in-order 32–bit RISC core, supported by a comprehensive state–of–the–art development toolset.

I’ve been contributing for more than 10 years in the various components of the STxP70 Toolset, incl. simulation, Nexus 5001™ tracing, and profiling software.

RISC-V

As of 2019, the RISC-V architecture is gaining a growing momentum, in both the academy and industry.

As a CPU IP provider, the Embedded Computing Solutions team investigated the opportunity to augment its portfolio with cores based on the open, royalty-free, RISC-V ISA.

In this regard, I actively took part to this evaluation.

  • Tour of the hardware implementations & software ecosystem,
  • Code size evaluation (gcc, clang, IAR), incl. the proposal for extra compressed instructions,
  • Instruction-Set Simulators survey, incl. feature and performance evaluation,
  • Hacking Spike, the RISC-V golden model (memory map, peripheral modeling, operand trace),
  • Hacking QEMU, the well-known CPU, performance virtual machine (memory map, peripheral modeling),
  • Porting Swerv-ISS to Win64,
  • Porting rv8 to Win64.

Taking advantage of Synopsys ASIP Designer, and leveraging the available tools, we successfully delivered both the RTL and the software toolchain in six weeks.

Intel® Atom™ processor wafer, courtesy Intel, Inc. (pressroom)

Profiling

When dealing with embedded computing, profiling aims at getting the most out of the system by iteratively assessing the execution, in order to enhance the software and/or the hardware, until the performance proves adequate.

In this respect, the STxP70 Toolset provides several profiling facilities, including the usual gprof and gcov, but also a non-intrusive (ie. instrumentation-less) profiler.

Re-engineering the legacy solution, and integrating our in–house STxP70 Objdump and .elf Reader, I specified, developed, verified and still maintains the STxP70 profiling framework.

  • The STxP70 Profiler features function profiling (both calltree and flat), instruction profiling, ISA profiling, plus stack and heap profiling, and computes statistics accordingly (total, count, min, max, mean, variance, std. deviation) whenever applicable to the dataset,
  • State-machine driven, the STxP70 Profiler detects function calls/returns (incl. exceptions), and reconstructs the calltree of the application,
  • I’ve proposed a multithreaded, SQLite3-based solution to handle the amount of data,
  • I’ve integrated the STxP70 Profiler to the STxP70 Simulators (both Instruction- and Cycle-Accurate), enabling the gathering of execution statistics out of our virtual prototyping platform,
  • I’ve integrated the STxP70 Profiler to the STxP70 Nexus framework, enabling the gathering of execution statistics out of our evaluation boards,
  • For ease of use, the STxP70  Profiler framework outputs the profiling results as CSV, HTML, XML, and/or CTF, and integrates seamlessly in Eclipse.

The STxP70 Profiler framework is currently actively maintained.

Nexus 5001™ Tracing

The Nexus 5001 Forum™ specifies a standard debug interface for embedded applications, facilitating runtime control (debugging), and trace capture (code and data).

Depending on its configuration, the STxP70 complies to IEEE-ISTO 5001™, providing a Nexus Class 2 program trace.

Integrating our in–house STxP70 Decoder and Disassembler, I specified, developed, verified and still maintains the STxP70 Nexus software framework.

  • State-machine driven, the trace reconstruction library correlates the Nexus messages with the .elf binary, feeding the STxP70 Toolset with the execution trace of the silicon target,
  • I’ve proposed an SQLite3–based solution to handle the amount of data, enabling quick and random access to the execution trace,
  • I’ve integrated the STxP70 Profiler to the STxP70 Nexus software framework, enabling calltree reconstruction and gathering of execution statistics,
  • Integrated to the QA platform, the STxP70 Nexus software framework has become the Golden Model for the verification of the VHDL of the STxP70 Nexus IP.

The STxP70 Nexus framework is currently actively maintained.

Simulation

In the STxP70 Architecture Team, I specified, developed, verified and still maintains the Instruction–Accurate Simulator of the STxP70, this latter being

  • The Golden Model for the verification of the VHDL of the STxP70 core,
  • The default execution vehicle delivered in the STxP70 Toolset,
  • The heart of the virtual prototyping platform of our Multicore System–On–Chip solutions,
  • The model of choice for architectural experiments.

Not only implementing the Instruction Set of the STxP70, the Instruction–Accurate Simulator of the STxP70 also

  • Supports micro–architectural features (configurability, eXtension interface, program and data caches, internal and external memory buses),
  • Models —to some extent— the cycle accuracy of the STxP70 pipeline,
  • And proposes advanced debug features, such as a detailed, functional trace, a Nexus 5001™ trace, a VCD trace, unlimited debug watchpoints (code and data), and a peripheral interface for basic system modelling.

Beside the Instruction–Accurate Simulator, I’m also in charge of the Cycle–Accurate Simulator, both of which being currently actively maintained.

Emulation

The ST100 was an innovative DSP, implementing a 16/32b four-issue instruction set, featuring an 11 pipeline stages core, and targeting embedded applications in custom system-on-chip products for demanding markets like cellular phones, hard disk drives, engine management units, telecommunication systems and advanced multimedia products.

I joined STMicroelectronics in July, 2001, integrating the ST100 Tools Team, in charge of the development of the Emulation Software driving the On-Chip Emulator of the ST100.

The Emulation Software :

  • Supported the whole ST100 family (ST100, ST120, ST122, and ST140),
  • Supported the whole feature set of the On-Chip Emulator of the ST100 (code and data download, memory inspection, execution control, hardware and software breakpoints, profiling, syscalls),
  • Was used as the reference to QA the VHDL of the On-Chip Emulator of the ST100 (using Celaro mappings),
  • Was shipped as a component of the ST100 Toolchain, providing debug access to the silicon targets implementing ST100 cores.

In 2005, STMicroelectronics ceased any further developments of the ST100 roadmap.

All this is now History.

Netstation Software

Along its offering of HP 9000 Unix systems, Hewlett-Packard introduced three successive, distinct families of Netstations —ie. RISC-based X terminals, namely the 700/X and 700/RX, the Envizex and Entria, and the Envizex II and Entria II— providing the client solution in the client/server computing scheme.

In 1998, Hewlett-Packard closed down the Panacom Automation Division located in Waterloo, Ontario (Canada), and transferred the second-level support of the HP Netstation Software to HP Grenoble, which in turn outsourced it to CAP Gemini.

In close co-operation with HP engineers, the transfer of the support activity occured in several steps, from in-depth training, to full ownership, including:

  • Rebuild from scratch of the Token Ring, ThinLAN and Ethernet networks, as well as re-install of the HP-PA Servers and Workstations, necessary for the QA,
  • Follow VxWorks and ClearCase (user and admin) courses,
  • Follow, debrief, and retro-document in-depth courses and/or informal talks provided by the HP engineers about the HP Netstation Software : i960 vs. MIPS specifics, the kernel and its drivers, the X11 server, the CDE window manager and the local clients, as well as general courses about BOOTP, DHCP, TFTP, NFS, XDMCP and X11 protocols, but also debugging techniques such as target attachment, kernel instrumentation, network trace dump, cross-compilation, and more,
  • Browse the various branches of source code, and compile debug and release binaries,
  • Produce installation images of the HP Netstation Software for the three product lines of X terminals.

After these six months of intensive training, I and teammates were able to:

  • Provide feedback and guidance to HP first level support,
  • Analyze and reproduce issues using the QA platform,
  • Debug and fix defects in the HP Netstation Software when necessary,
  • Provide patches delivered within the official HP-UX Software Depot.

On January 31, 2004, Hewlett-Packard ceased official support for Netstations.

All this is now History.

HP 9000 712/60 by Blake Patterson – Used under CC-BY 2.0 (remix)

Trainings

2023 Rust
2021 ARM v8-M Architecture
ARM v7-M Architecture Introduction
2019 Cryptographic Engineering
2018 Python
2017 Confidentality & Information Security Awareness
STM32 & Nucleo Boards
2016 Synopsys ASIP Designer
2015 Security Awareness in Product Development
2013 Git
2012 TLM/SystemC Virtual Prototyping
2010 Embedded LinuxProgramming
Linux Kernel Mode & Drivers
2008 Perl
2006 Cadence XtensaTensilica
2005 SystemC
TLM/SystemC
2004 CoWare LISA
2002 ST100 Toolset
2000 Unified Modeling Language
1999 WindRiver VxWorks